Accumulator

module accum (C, CLR, D, Q);
  input C, CLR;
  input [3:0] D;
  output [3:0] Q;
  reg [3:0] tmp;
    always @(posedge C or posedge CLR)
   
    begin if (CLR) tmp = 4'b0000;
    else tmp = tmp + D;
    end
    assign Q = tmp;
    endmodule