Up counter & Down counter

module counterup(clock,reset,count);
  input clock,reset;
  output[3:0]count;
  reg[3:0] count;
  always@(posedge clock)
  begin
    if(reset)
      count=4'b0000;
    else
      count=count+1;
    end
  endmodule
 
  module counterdown(clock,reset,count);
  input clock,reset;
  output[3:0]count;
  reg[3:0] count;
  always@(posedge clock)
  begin
    if(reset)
      count=4'b1111;
    else
      count=count-1;
    end
  endmodule