Accumulator

module accum (C, CLR, D, Q);
  input C, CLR;
  input [3:0] D;
  output [3:0] Q;
  reg [3:0] tmp;
    always @(posedge C or posedge CLR)
   
    begin if (CLR) tmp = 4'b0000;
    else tmp = tmp + D;
    end
    assign Q = tmp;
    endmodule

PRBS (Pseudo random binary sequence)

module prbs(a,clk,clr);
output [3:0] a;
input clk,clr;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if(clr)
begin
tmp = 4'b1111;
end
else
begin
tmp = { tmp[0]^tmp[1],tmp[3],tmp[2],tmp[1]};
end
end
assign a=tmp;
endmodule

UpDown counter

module counterupdown(clock,reset,count,s);
  input clock,reset,s;
  output[2:0]count;
  reg[2:0] count;
  always@(posedge clock)
  begin
   if(s==0)
     if(reset)
       count=3'b000;
     else
       count=count+1;
   else if(s==1)
     if(reset)
       count=3'b111;
     else
       count=count-1;
  end
 endmodule

Up counter & Down counter

module counterup(clock,reset,count);
  input clock,reset;
  output[3:0]count;
  reg[3:0] count;
  always@(posedge clock)
  begin
    if(reset)
      count=4'b0000;
    else
      count=count+1;
    end
  endmodule
 
  module counterdown(clock,reset,count);
  input clock,reset;
  output[3:0]count;
  reg[3:0] count;
  always@(posedge clock)
  begin
    if(reset)
      count=4'b1111;
    else
      count=count-1;
    end
  endmodule

Flip Flops

SR flip flop
module rsff(q,q0,clock,reset,s,r);
  input s,r,clock,reset;
  output q=0,q0;
  reg q;
  always@(posedge clock)
  begin
    if(reset)
      q=0;
    else if(r==0&&s==0)
      q=q;
    else if(r==1&&s==1)
      q="x";
    else
      q=s;
    end
    assign q0=~q;
  endmodule

JK flip flop

module jkff(q,q0,clock,reset,j,k);
  input clock,reset,j,k;
  output q=0,q0;
  reg q;
  always@(posedge clock)
  begin
    if(reset)
      q=0;
  else if(j==0&&k==0)
      q=q;
    else if(j==1&&k==1)
      q=~q;
    else
      q=j;
    end
    assign q0=~q;
  endmodule

D-Flip flop

module dff(clock,reset,data,q,qbar);
  input clock,reset,data;
  output q,qbar;
  reg q;
  always @ (posedge clock)
  begin
    if(reset)
      q=0;
    else
      q=data;
    end
    assign qbar=~q;
  endmodule

T flip flop
module tff(q,q0,clock,t,reset);
  input clock,reset,t;
  output q=0,q0;
  reg q;
  always@(posedge clock)
  begin
    if(reset)
      q=0;
    else if(t)
      q=~q;
    end
    assign q0=~q;
  endmodule

multiplier

module ha(sout,cout,a,b);
input a,b;
output sout,cout;
assign sout=a^b;
assign cout=a&b;
endmodule
module fa(sout,cout,a,b,c);
input a,b,c;
output sout,cout;
assign sout=a^b^c;
assign cout=a&b|b&c|c&a;
endmodule
module multi88(p,a,b);
input[3:0] a,b;
output[7:0]p;
wire[17:0]x ;
assign p[0]=a[0]&b[0];
ha e1(p[1],x[1],(a[1]&b[0]),(b[1]&a[0]));
fa e2(x[2],x[3],x[1],(b[1]&a[1]),(b[2]&a[0]));
fa e3(x[4],x[5],x[3],(b[2]&a[1]),(b[3]&a[0]));
ha e4(x[7],x[6],x[5],(b[3]&a[1]));
ha e5(p[2],x[8],x[2],(b[0]&a[2]));
fa e6(x[9],x[10],x[8],x[4],(b[1]&a[2]));
fa e7(x[11],x[12],x[10],x[7],(b[2]&a[2]));
fa e8(x[13],x[14],x[12],x[6],(b[3]&a[2]));
ha e9(p[3],x[15],x[9],(b[0]&a[3]));
fa e10(p[4],x[16],x[15],x[11],(b[1]&a[3]));
fa e11(p[5],x[17],x[16],x[13],(b[2]&a[3]));
fa e12(p[6],p[7],x[14],x[17],(b[3]&a[3]));
endmodule